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ltc4098-3.6 409836f usb compatible switching power manager/lifepo 4 charger with overvoltage protection the ltc ? 4098-3.6 is a high effciency usb powerpath controller and full-featured lifepo 4 battery charger. it seam - lessly manages power distribution from multiple sources including usb, wall adapter, automotive, firewire or other high voltage dc/dc converters, and a lifepo 4 battery. the ltc4098-3.6 charge algorithm is optimized for lifepo 4 by implementing a 1-hour foat voltage termination timer and a 0c to 60c ntc-based charge qualifcation range. furthermore, completely discharged batteries are charged at the full programmed charge current. the ltc4098-3.6s switching regulator can automatically limit its input current for usb compatibility. for automo - tive and other high voltage applications, the ltc4098 -3.6 interfaces with an external switching regulator. both the usb input and the auxiliary input controller feature bat- track optimized charging to provide maximum power to the application and reduced heat in high power density ap - plications with input supplies from 5v to as high as 38v. an overvoltage protection circuit guards the ltc4098-3.6 from high voltage damage on the vbus pin with just two external components. the ltc4098-3.6 is available in a 20-lead 3mm 4mm 0.75mm qfn surface mount package. n high peak power battery-powered equipment n backup applications n high reliability handhelds n switching regulator with bat-track tm adaptive output control makes optimal use of limited power available from usb port to charge battery and power application n charge control algorithm specifcally designed for lifepo 4 (lithium iron phosphate) n overvoltage protection guards against damage n bat-track external step-down switching regulator control maximizes effciency from automotive, firewire and other high voltage input sources n 180m internal ideal diode plus external ideal diode controller seamlessly provide low loss powerpath tm when input power is limited or unavailable n preset 3.6v charge voltage with 0.5% accuracy n instant-on operation with discharged battery n 700ma maximum load current from usb port n 2a maximum input current from internal switching regulator n 1.5a maximum charge current with thermal limiting n 20-lead 3mm 4mm 0.75mm qfn package high effciency usb compatible lifepo 4 battery charger with overvoltage protection v bus 10f 0.1f 3.01k 500 10f 3.3h 6.04k 5v/usb to c system load 409836 ta01a clprog prog ltc4098-3.6 gnd sw batsens ovgate ovsens d0-d2 bat v out lifepo 4 + 3 reduced power dissipation vs linear battery charger battery voltage (v) 2.70 0 power dissipation (w) 0.5 1.0 1.5 2.0 3.0 2.85 3.00 3.15 3.30 409836 ta01b 3.45 3.60 2.5 v in = 5v prog = 500 i chrg = 1.1a 10x mode switching battery charger linear battery charger additional power available for charging typical a pplica t ion fea t ures a pplica t ions descrip t ion l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and bat track and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc4098-3.6 409836f elec t rical c harac t eris t ics v bus , wall (transient) t < 1ms, duty cycle < 1% .......................................... C0.3v to 7v v bus , wall (static), bat, batsens, chrg , ntc, ................................................. C0.3v to 6v d0, d1, d2 ......... C0.3v to max (v bus , v out , bat) + 0.3v i ovsens ................................................................. 10ma i clprog .................................................................... 3ma i prog ........................................................................ 2ma i chrg ...................................................................... 50ma i vout , i sw , i bat ....................................................... 2.25a i acpr ...................................................................... 5ma operating temperature range .................. C40c to 85c junction temperature ........................................... 125c storage temperature range ................... C65c to 125c (notes 1, 3) the l denotes the specifcations which apply over the full operating temp- erature range, otherwise specifcations are at t a = 25c (note 2). v bus = 5v, bat = 3.3v, r clprog = 3.01k, unless otherwise noted. symbol parameter conditions min typ max units input power supply v bus input supply voltage l 4.35 5.5 v i vbus(lim) total input current 1x mode 5x mode 10x mode low power suspend mode high power suspend mode l l l l l 92 445 815 0.32 1.6 96 473 883 0.39 2.05 100 500 1000 0.5 2.5 ma ma ma ma ma i vbusq (note 4) input quiescent current 1x mode 5x mode 10x mode low power suspend mode high power suspend mode 6 15 15 0.042 0.042 ma ma ma ma ma h clprog (note 4) ratio of measured v bus current to clprog program current 1x mode 5x mode 10x mode low power suspend mode high power suspend mode 230 1164 2210 11.6 60 ma/ma ma/ma ma/ma ma/ma ma/ma p in con f i g ura t ion 20 19 18 17 7 8 top view 21 gnd udc package 20-lead (3mm s 4mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 ovsens ovgate clprog ntcbias ntc batsens d1 d0 sw v bus v out bat v c acpr wall d2 prog chrg gnd idgate t jmax = 125c, q ja = 43c/w exposed pad (pin 21) is gnd, must be soldered to pcb or d er in f orma t ion lead free finish tape and reel part marking package description temperature range ltc4098eudc-3.6#pbf ltc4098eudc-3.6#trpbf lfyr 20-lead (3mm s 4mm) plastic qfn C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ a b solu t e ma x imum ra t in g s
ltc4098-3.6 409836f symbol parameter conditions min typ max units i vout v out current available before discharging battery 1x mode 5x mode 10x mode low power suspend mode high power suspend mode 135 659 1231 0.32 2.04 ma ma ma ma ma v clprog clprog servo voltage in current limit 1x, 5x, 10x modes suspend modes 1.188 100 v mv v uvlo v bus undervoltage lockout rising threshold falling threshold 3.95 4.30 4.00 4.35 v v v out v out voltage 1x, 5x, 10x modes, 0v < bat 3.6v, i vout = 0ma, battery charger off 3.1 bat + 0.4 4.3 v usb suspend modes, i vout = 250a 3.7 3.8 3.9 v f osc switching frequency 1.96 2.25 2.65 mhz r pmos pmos on-resistance 0.18 r nmos nmos on-resistance 0.30 i peak peak inductor current clamp 1x mode 5x mode 10x mode 1.2 1.7 3 a a a r susp suspend ldo output resistance 15 bat-track external switching regulator control v wall absolute wall input threshold rising threshold falling threshold 4.1 4.25 3.2 4.4 v v d v wall differential wall input threshold wall-bat rising threshold wall-bat falling threshold 0 90 25 50 mv mv regulation target 3.5 bat + 0.4 v wall quiescent current 100 a acpr high voltage i acpr = 0ma v out v acpr low voltage i acpr = 0ma 0 v overvoltage protection v ovp overvoltage protection threshold rising threshold, r ovsens = 6.04k 6.10 6.35 6.70 v v ovgate ovgate output voltage input below v ovp input above v ovp 1.88 ? v ovsense 0 12 v v t rise ovgate time to reach regulation c ovgate = 1nf 2.2 ms battery charger v float bat regulated output voltage 0c t a 85c 3.582 3.565 3.6 3.6 3.618 3.635 v v i chg constant-current mode charge current r prog = 1k, 10x mode r prog = 5k, 5x, 10x modes 980 192 1030 206 1080 220 ma ma i bat battery drain current v bus > v uvlo , powerpath switching regulator on, battery charger off, i vout = 0a 3.7 5 a v bus = 0v, i vout = 0a (ideal diode mode) 25 35 a v prog prog pin servo voltage 1.000 v h prog ratio of i bat to prog pin current 1030 ma/ma v rechrg recharge battery threshold voltage threshold voltage relative to v float C80 C100 C120 mv elec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temp- erature range, otherwise specifcations are at t a = 25c (note 2). v bus = 5v, bat = 3.3v, r clprog = 3.01k, unless otherwise noted.
ltc4098-3.6 409836f symbol parameter conditions min typ max units t term safety timer termination period timer starts when bat = v float 0.85 1 1.15 hour t badbat bad battery termination time bat < v trkl 0.43 0.5 0.58 hour h c/10 end of charge indication current ratio (note 5) 0.09 0.1 0.11 ma/ma v chrg chrg pin output low voltage i chrg = 5ma 65 100 mv i chrg chrg pin input current bat = 4.5v, v chrg = 5v 0 1 a r on_chg battery charger power fet on-resistance (between v out and bat) i bat = 200ma 0.18 t lim junction temperature in constant- temperature mode 110 c ntc v cold cold temperature fault threshold voltage rising threshold hysteresis 75.0 76.5 2.9 78.0 %ntcbias %ntcbias v hot hot temperature fault threshold voltage falling threshold hysteresis 18.4 19.9 1.9 21.4 %ntcbias %ntcbias v dis ntc disable threshold voltage falling threshold hysteresis 0.5 1.3 50 2.3 %ntcbias mv i ntc ntc leakage current ntc = 5v C50 50 na ideal diode v fwd forward voltage detection i vout = 10ma 15 mv r dropout internal diode on-resistance, dropout i vout = 200ma 0.18 i max diode current limit 2 a logic (d0, d1, d2) v il input low voltage 0.4 v v ih input high voltage 1.2 v i pd static pull-down current v pin = 1v 2 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc4098e-3.6 is tested under pulsed load conditions such that t j t a . the ltc4098e-3.6 is guaranteed to meet performance specifcations from 0c to 85c. specifcations over the C 40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: the ltc4098e-3.6 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specifed maximum operating junction temperature may impair device reliability. note 4: total input current is: i vbusq + (v clprog /r clprog ) ? (h clprog + 1) note 5: h c/10 is expressed as a fraction of measured full charge current with a 5k prog resistor. elec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temp- erature range, otherwise specifcations are at t a = 25c (note 2). v bus = 5v, bat = 3.3v, r clprog = 3.01k, unless otherwise noted.
ltc4098-3.6 409836f t ypical per f ormance c harac t eris t ics forward voltage (v) 0 diode current (a) 0.6 0.8 1.0 0.16 409836 g01 0.4 0.2 0 0.04 0.08 0.12 0.20 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode only battery voltage (v) 2.7 diode resistance ( 7 ) 0.15 0.20 0.25 3.9 409836 g02 0.10 0.05 0 3.0 3.3 3.6 4.2 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode battery voltage (v) 2.7 750 409836 g03 700 650 3.0 3.3 3.6 600 550 load current (ma) v bus = 5v r clprog = 3.01k 5x usb setting ideal diode v-i characteristics ideal diode resistance vs battery voltage v out voltage vs v out current (battery charger disabled) usb compliant load current available before discharging battery t a = 25c, unless otherwise noted. output current (ma) 0 output voltage (v) 4.00 4.25 800 409836 g04 3.75 3.50 3.25 3.00 200 400 600 bat = 3.6v bat = 3.3v v bus = 5v 5x usb setting battery voltage (v) 2.7 150 409836 g07 140 130 3.0 3.3 3.6 120 110 load current (ma) v bus = 5v r clprog = 3.01k 1x usb setting usb compliant load current available before discharging battery 2.7 500 600 700 409836 g08 400 300 3.0 3.3 3.6 200 100 0 charge current (ma) v bus = 5v r prog = 1k r clprog = 3.01k 5x usb setting battery voltage (v) 2.7 100 120 140 409836 g09 80 60 3.0 3.3 3.6 40 20 0 charge current (ma) v bus = 5v r prog = 1k r clprog = 3.01k 1x usb setting battery voltage (v) usb limited battery charge current vs battery voltage usb limited battery charge current vs battery voltage output current (ma) 0 output voltage (v) 3.25 3.50 409836 g05 3.00 2.75 200 400 600 800 3.75 v bus = 5v bat = 3v r clprog = 3.01k r prog = 2k 5x usb setting output current (ma) 0 charge current (ma) 150 450 409836 g06 0 300 ?150 ?300 200 400 600 800 600 v bus = 5v bat = 3v r clprog = 3.01k r prog = 2k 5x usb setting battery charge current vs v out current (battery charger enabled) v out voltage vs v out current (battery charger enabled)
ltc4098-3.6 409836f battery charge current vs temperature normalized battery charger float voltage vs temperature v out voltage vs v out current in suspend v bus current vs v out current in suspend (includes ovp) automatic battery charge current vs output voltage output current (ma) 0 output voltage (v) 3.45 3.60 3.90 3.75 2.0 409836 g14 3.30 3.15 3.00 0.5 1.0 1.5 2.5 suspend high suspend low v bus = 5v bat = 3.3v r clprog = 3.01k output current (ma) 0 v bus current (ma) 1.5 2.0 2.5 2.0 409836 g15 1.0 0.5 0 0.5 1.0 1.5 2.5 suspend high suspend low v bus = 5v bat = 3.3v r clprog = 3.01k temperature (c) ?40 0 charge current (ma) 100 200 300 400 0 40 80 120 409836 g17 500 600 ?20 20 60 100 thermal regulation r prog = 2k temperature (c) ?40 normalized float voltage 60 409836 g18 0.997 ?15 10 35 85 1.003 1.002 1.001 1.000 0.999 0.998 output voltage (v) 0 % programmed charge current 20 40 60 80 100 120 3.1 3.2 3.3 3.4 409836 g16 3.5 battery charging effciency vs battery voltage with no external load (p bat /p vbus ) v bus current vs v bus voltage (suspend modeincludes ovp) battery voltage (v) efficiency (%) 80 90 409836 g12 70 60 100 r clprog = 3.01k r prog = 1k i vout = 0ma 1x charging efficiency 5x charging efficiency 2.7 3.0 3.3 3.6 v bus voltage (v) 1 v bus current (a) 60 80 100 5 409836 g13 40 20 0 2 3 4 6 bat = 3.3v i vout = 0ma t a = 25c, unless otherwise noted. t ypical per f ormance c harac t eris t ics powerpath switching regulator effciency vs output current battery drain current vs battery voltage battery voltage (v) 2.7 0 battery current (a) 5 10 15 20 25 30 3.0 3.3 3.6 409836 g10 v bus = 0v v bus = 5v (suspend mode) i vout = 0a output current (a) 0.01 40 efficiency (%) 50 60 70 80 100 0.1 1 409836 g11 90 5x, 10x mode 1x mode bat = 3.3v
ltc4098-3.6 409836f chrg pin voltage (v) 0 chrg pin current (ma) 60 80 100 4 409836 g23 40 20 0 1 2 3 5 v bus = 5v bat = 3.8v oscillator frequency vs temperature v bus quiescent current vs temperature quiescent current in suspend vs temperature low battery (instant-on, charger disabled) output voltage vs temperature temperature (c) ?40 output voltage (v) 3.54 3.56 60 409836 g19 3.52 3.50 ?15 10 35 110 85 3.58 bat = 2.7v i vout = 100ma 5x mode temperature (c) ?40 oscillator frequency (mhz) 2.25 2.35 2.30 60 409836 g20 2.20 2.15 2.10 ?15 10 35 85 temperature (c) ?40 2 quiescent current (ma) 5 8 11 14 17 20 ?15 ?10 35 60 409836 g21 85 v bus = 5v i vout = 0a 5x mode 1x mode temperature (c) ?40 27 quiescent current (a) 30 33 36 39 42 45 ?15 10 35 60 409836 g22 85 v bus = 5v i vout = 0a chrg pin current vs voltage (pull-down state) ovp connection waveform i out 500a/div 0ma 500s/div 409836 g24 v out 20mv/div ac-coupled suspend ldo transient response (500a to 1.5ma) v bus 5v/div ovgate 5v/div 500s/div 409836 g25 ovp input voltage 0v to 5v step 5v/div t a = 25c, unless otherwise noted. t ypical per f ormance c harac t eris t ics
ltc4098-3.6 409836f ovgate vs ovsens rising overvoltage threshold vs temperature temperature (c) ?40 ovp threshold (v) 6.270 6.275 6.280 60 409836 g29 6.265 6.260 6.255 ?15 10 35 85 input voltage (v) 0 0 ovgate voltage (v) 2 4 6 8 10 12 2 4 6 8 409836 g30 ovsens connected to input through 6.04k resistor ovsens quiescent current vs temperature temperature (c) ?40 quiescent current (a) 33 35 37 60 409836 g28 31 29 27 ?15 10 35 85 v ovsens = 5v t a = 25c, unless otherwise noted. t ypical per f ormance c harac t eris t ics ovp protection waveform v bus 5v/div ovgate 5v/div 500s/div 409836 g26 ovp input voltage 5v to 10v step 5v/div v bus 5v/div ovgate 5v/div 500s/div 409836 g27 ovp input voltage 10v to 5v step 5v/div ovp reconnection waveform
ltc4098-3.6 409836f ovsens (pin 1): overvoltage protection sense input. o vsens should be connected through a 6.04k resistor to the input power connector and the drain of an external n-channel mosfet pass transistor. when the voltage on this pin exceeds a preset level, the ovgate pin will be pulled to gnd to disable the pass transistor and protect downstream circuitry. if overvoltage protection is not desired, connect ovsens to gnd. ovgate (pin 2): overvoltage protection gate output. connect ovgate to the gate pin of an external n-chan - nel mosfet pass transistor. the source of the transistor should be connected to v bus and the drain should be connected to the products dc input connector. this pin is connected to an internal charge pump capable of creating suffcient overdrive to fully enhance the pass transistor. if an overvoltage condition is detected, ovgate is brought rapidly to gnd to prevent damage to downstream circuitry. ovgate works in conjunction with ovsens to provide this protection. if overvoltage protection is not desired, leave ovgate open. clprog (pin 3): usb current limit program and monitor pin. a 1% resistor from clprog to ground determines the upper limit of the current drawn from the v bus pin. a precise fraction of the input current, h clprog , is sent to the clprog pin when the high side switch is on. the switching regulator delivers power until the clprog pin reaches 1.188v. therefore, the current drawn from v bus will be limited to an amount given by h clprog and r clprog . there are several ratios for h clprog available, two of which correspond to the 500ma and 100ma usb specifcations. a multilayer ceramic averaging capacitor is also required at clprog for fltering. ntcbias (pin 4): ntc thermistor bias output. if ntc operation is desired, connect a bias resistor between ntcbias and ntc, and an ntc thermistor between ntc and gnd. to disable ntc operation, connect ntc to gnd and leave ntcbias open. ntc (pin 5): input to the ntc thermistor monitoring circuits. the ntc pin connects to a negative temperature coeffcient thermistor which is typically co-packaged with the battery pack to determine if the battery is too hot or too cold to charge. if the batterys temperature is out of range, charging is paused until the battery temperature re-enters the valid range. a low drift bias resistor is required from ntcbias to ntc and a thermistor is required from ntc to ground. if the ntc function is not desired, the ntc pin should be grounded. batsens (pin 6): battery voltage sense input. for proper operation, this pin must always be connected to bat. for best performance, connect batsens to bat physically close to the lifepo 4 cell. prog (pin 7): charge current program and charge cur - rent monitor pin. connecting a 1% resistor from prog to ground programs the charge current. if suffcient input power is available in constant-current mode, this pin servos to 1v. the voltage on this pin always represents the actual charge current by using the following formula: i v r bat p rog p rog = ? 1030 chrg (pin 8): open-drain charge status output. the chrg pin indicates the status of the battery charger. four possible states are represented by chrg : charging, not charging, unresponsive battery and battery temperature out of range. chrg is modulated at 35khz and switches between a low and a high duty cycle for easy recognition by either humans or microprocessors. chrg requires a pull-up resistor and/or led to provide indication. gnd (pin 9, exposed pad pin 21): the exposed pad and pin must be soldered to the pcb to provide a low electrical and thermal impedance connection to ground. idgate (pin 10): ideal diode amplifer output. this pin controls the gate of an external p-channel mosfet transis - tor used to supplement the internal ideal diode. the source of the p-channel mosfet should be connected to v out and the drain should be connected to bat. bat (pin 11): single-cell lifepo 4 battery pin. depending on available power and load, a lifepo 4 battery on bat will either deliver system power to v out through the ideal diode or be charged from the battery charger. the ltc4098-3.6 will charge to a foat voltage of 3.600v. v out (pin 12): output voltage of the switching powerpath controller and input voltage of the battery charger. the pin f unc t ions
ltc4098-3.6 0 409836f majority of the portable product should be powered from v out . the ltc4098-3.6 will partition the available power between the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out is powered even if the load exceeds the allotted power from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance multilayer ceramic capacitor. v bus (pin 13): input voltage for the switching powerpath controller. v bus will usually be connected to the usb port of a computer or a dc output wall adapter. v bus should be bypassed with a low impedance multilayer ceramic capacitor. sw (pin 14): the sw pin delivers power from v bus to v out via the step-down switching regulator. an inductor should be connected from sw to v out . see the applica - tions information section for a discussion of inductance value and current rating. d0 (pin 15): mode select input pin. d0, in combination with the d1 pin and the d2 pin, controls the current limit and battery charger functions of the ltc4098-3.6 (see table 1). this pin is pulled low by a weak current sink. d1 (pin 16): mode select input pin. d1, in combination with the d0 pin and the d2 pin, controls the current limit and battery charger functions of the ltc4098-3.6 (see table 1). this pin is pulled low by a weak current sink. d2 (pin 17): mode select input pin. d2, in combination with the d0 pin and d1 pin, controls the current limit and battery charger functions of the ltc4098-3.6 (see table 1). this pin is pulled low by a weak current sink. wall (pin 18): external power source sense input. wall should be connected to the output of the external high voltage switching regulator and to the drain of an exter - nal p-channel mosfet transistor. it is used to determine when power is applied to the external regulator. when power is detected, acpr is driven low and the usb input is automatically disabled. acpr (pin 19): external power source present output (active low). acpr indicates that the output of the external high voltage step-down switching regulator is suitable for use by the ltc4098-3.6. it should be connected to the gate of an external p-channel mosfet transistor whose source is connected to v out and whose drain is connected to wall. acpr has a high level of v out and a low level of gnd. v c (pin 20): bat-track external switching regulator control output. this pin drives the v c pin of a linear technology external step-down switching regulator. in concert with wall and acpr , it will regulate v out to maximize battery charger effciency. pin f unc t ions
ltc4098-3.6 409836f 15 5 + ? + ? + ? + ? + ? + ? + ? 0.1v undertemp average input current limit controller overtemp ntc ntcbias v out ntc t 3 clprog 13 v bus 2 ovgate 1 ovsens ntc fault d1 ntc enable 16 d2 17 d0 logic 1.188v + ? + + ? average output voltage limit controller osc pwm s pwm 3.8v s 2 100mv 6v overvoltage protection suspend ldo i ld o / m i switc h / n to usb or wall adpapter q r 3.5v 0.4v 1v 100mv ntc 409836 bd i bat /1030 + ? + ? prog 7 gnd 21 8 11 bad cell chrg bat batsens single-cell lifepo 4 optional external ideal diode pmos 10 idgate 12 v out to system load acpr constant-current constant-voltage battery charger + ? 0v 15mv ideal diode + ? bat + 0.4v 3.6v v out 4.3v + + ? + ? 14 sw 19 wall nonoverlap and drive logic gnd 9 + v c 6 4 + ? to automotive, firewire, etc. sw i sense v in v c v out hvok lt3653 18 20 b loc k d ia g ram
ltc4098-3.6 409836f introduction the ltc4098-3.6 is a high effciency power management and lifepo 4 charger solution designed to make optimal use of the power available from a variety of sources, while minimizing power dissipation and easing thermal budgeting constraints. the innovative powerpath architecture ensures that the application is powered immediately after external voltage is applied, even with a completely dead battery, by prioritizing power to the application over the battery. the ltc4098-3.6 includes a bat-track monolithic step- down switching regulator for usb, wall adapters and other 5v sources. designed specifcally for usb applications, the switching regulator incorporates a precision average input current limit for usb compatibility. because power is conserved, the ltc4098-3.6 allows the load current on v out to exceed the current drawn by the usb port, making maximum use of the allowable usb power for battery charging. the switching regulator and battery charger communicate to ensure that the average input current never exceeds the usb specifcations. for automotive, firewire, and other high voltage appli- cations, the ltc4098-3.6 provides bat-track control of an external ltc step-down switching regulator to maximize battery charger effciency and minimize heat production. when power is available from both the usb and high voltage inputs, the high voltage input is prioritized and the usb input is automatically disabled. the ltc4098-3.6 features an overvoltage protection circuit which is designed to work with an external n-channel mosfet to prevent damage to its inputs caused by ac - cidental application of high voltage. the ltc4098-3.6 contains both an internal 180m ideal diode and an ideal diode controller designed for use with an external p-channel mosfet. the ideal diodes from bat to v out guarantee that ample power is always available to v out even if there is insuffcient or absent power at v bus or wall. finally, to prevent battery drain when a device is connected to a suspended usb port, an ldo from v bus to v out provides either low power or high power usb suspend current to the application. bat-track input current limited step down switching regulator the power delivered from v bus to v out is controlled by a 2.25mhz constant-frequency step-down switching regulator. to meet the usb maximum load specifcation, the switching regulator contains a measurement and control system that ensures that the average input cur - rent remains below the level programmed at clprog. v out drives the combination of the external load and the battery charger. if the combined load does not cause the switching power supply to reach the programmed input current limit, v out will track approximately 0.4v above the battery voltage. by keeping the voltage across the bat - tery charger at this low level, power lost to the battery charger is minimized. figure 1 shows the power path components. if the combined external load plus battery charge current is large enough to cause the switching power supply to reach the programmed input current limit, the battery charger will reduce its charge current by precisely the amount necessary to enable the external load to be satisfed. even if the battery charge current is programmed to exceed the allowable usb current, the usb specifcation for average input current will not be violated; the battery charger will reduce its current as needed. furthermore, if the load current at v out exceeds the programmed power from v bus , load current will be drawn from the battery via the ideal diodes even when the battery charger is enabled. the current at clprog is a precise fraction of the v bus current. when a programming resistor and an averaging capacitor are connected from clprog to gnd, the voltage on clprog represents the average input current of the switching regulator. as the input current approaches the programmed limit, clprog reaches 1.188v and power delivered by the switching regulator is held constant. several ratios of current are available which can be set to correspond to usb low and high power modes with a single programming resistor. opera t ion
ltc4098-3.6 409836f + ? + + ? 0.4v 1.188v 3.5v clprog i switc h / n + ? + ? 15mv omv ideal diode pwm and gate drive average input current limit controller average output voltage limit controller constant-current constant-voltage battery charger + ? 3 idgate 10 v out 12 sw 3.1v to (bat + 0.4v) to system load optional external ideal diode pmos single-cell lifepo 4 40981 f01 14 bat 11 batsens from usb or wall adapter 13 + 2 ovgate v bus ovsens to automotive, firewire, etc. acpr bat + 0.4v 3.6v v out 4.3v + + ? + ? 19 wall bat-track hv control 18 v c 20 sw i sense v in v c v out hvok lt3653 6 s 2 6v overvoltage protection + ? + ? 1 usb input battery power hv input figure 1. simplifed power flow diagram opera t ion
ltc4098-3.6 409836f the input current limit is programmed by various com - binations of the d0, d1 and d2 pins as shown in table 1. the switching input regulator can also be deactivated (usb suspend). the average input current will be limited by the clprog programming resistor according to the following expression: i i v r h vbu s vbu sq cl p rog cl p rog cl p rog = + + ( ) ? 1 where i vbusq is the quiescent current of the ltc4098 -3.6, v clprog is the clprog servo voltage in current limit, r clprog is the value of the programming resistor and h clprog is the ratio of the measured current at v bus to the sample current delivered to clprog. refer to the electrical characteristics table for values of h clprog , v clprog and i vbusq . given worst-case circuit tolerances, the usb specifcation for the average input current in 1x or 5x mode will not be violated, provided that r clprog is 3.01k or greater. table 1 shows the available settings for the d0, d1 and d2 pins. table 1. controlled input current limit d2 d1 d0 charger status i bus(lim) 0 0 0 on 100ma (1x) 0 0 1 on 1a (10x) 0 1 0 on 500ma (5x) 0 1 1 off 500a (susp low) 1 0 0 off 100ma (1x) 1 0 1 off 1a (10x) 1 1 0 off 500ma (5x) 1 1 1 off 2.5ma (susp high) bat (v) 2.4 4.0 3.8 3.4 3.2 3.0 2.8 2.6 2.4 3.3 409836 f02 3.6 2.7 3.0 3.6 v out (v) no load 400mv figure 2. v out vs bat notice that when d0 is high and d1 is low, the switching regulator is set to a higher current limit for increased charging and power availability at v out . these modes will typically be used when there is line power available from a wall adapter. while not in current limit, the switching regulators bat-track feature will set v out to approximately 400mv above the voltage at bat. however, if the voltage at bat is below 3.1v, and the load requirement does not cause the switching regulator to exceed its current limit, v out will regulate at a fxed 3.5v, as shown in figure 2. this instant-on operation will allow a portable product to run immediately when power is applied without waiting for the battery to charge. if the load does exceed the current limit at v bus , v out will range between the no-load voltage and slightly below the battery voltage, indicated by the shaded region of figure 2. opera t ion
ltc4098-3.6 409836f for very low battery voltages, the battery charger acts like a load and, due to limited input power, its current will tend to pull v out below the 3.5v instant-on voltage. to prevent v out from falling below this level, an undervoltage circuit automatically detects that v out is falling and reduces the battery charge current as needed. this reduction ensures that load current and voltage are always prioritized while allowing as much battery charge current as possible. refer to overprogramming the battery charger in the applica - tions information section. the voltage regulation loop compensation is controlled by the capacitance on v out . an mlcc capacitor of 10f is required for loop stability. additional capacitance beyond this value will improve transient response. an internal undervoltage lockout circuit monitors v bus and keeps the switching regulator off until v bus rises above the rising uvlo threshold (4.3v). if v bus falls below the falling uvlo threshold (4v), system power at v out will be drawn from the battery via the ideal diodes. bat-track high voltage external switching regulator control the wall, acpr and v c pins can be used in conjunction with an external high voltage step-down switching regulator such as the lt3653 or lt3480 to minimize heat production when operating from higher voltage sources, as shown in figures 3 and 4. bat-track control circuitry regulates the external switching regulators output voltage to the larger of bat + 400mv or 3.6v. this maximizes battery charger ef fciency while still allowing instant-on operation when the battery is deeply discharged. when using the lt3480, the feedback network should be set to generate an output voltage between 4.5v and 5.5v. when high voltage is applied to the external regulator, wall will rise toward this programmed output voltage. when wall exceeds approximately 4.3v, acpr is brought low and the bat-track control of the ltc4098-3.6 overdrives the local v c control of the external high voltage step-down switching regulator. therefore, once the bat-track control is enabled, the output voltage is set independent of the switching regulator feedback network. bat-track control provides a signifcant effciency advantage over the simple use of a 5v switching regulator output to drive the battery charger. with a 5v output driving v out , battery charger effciency is approximately: h h to ta l b uc k bat v v = ? 5 where h buck is the effciency of the high voltage switching regulator and 5v is the output voltage of the switching regulator. with a typical switching regulator effciency of 87% and a typical battery voltage of 3.4v, the total battery charger effciency is approximately 59%. assuming a 1a charge current, well over 2w of power is dissipated just to charge the battery! with bat-track, battery charger effciency is approximately: h h to ta l b uc k bat bat v = + ? . 0 4 opera t ion acpr 409836 f03 ltc4098-3.6 v out v out i sense wall v c lt3653 v c hvok system load sw acpr 409836 f04 ltc4098-3.6 v out wall v c lt3480 v c system load sw fb figure 3. lt3653 typical interface figure 4. lt3480 typical interface
ltc4098-3.6 409836f with the same assumptions as previously stated, the total battery charger effciency is approximately 78%. this example works out to just over 1w of power dissipation, or almost 50% less heat. see the typical applications section for complete circuits using the lt3653 and lt3480 with bat-track control. overvoltage protection the ltc4098-3.6 can protect itself from the inadvertent application of excessive voltage to v bus or wall with just two external components: an n-channel mosfet and a 6.04k resistor. the maximum safe overvoltage magnitude will be determined by the choice of the external n-channel mosfet and its associated drain breakdown voltage. the overvoltage protection module consists of two pins. the frst, ovsens, is used to measure the externally ap - plied voltage through an external resistor. the second, ovgate, is an output used to drive the gate pin of an external fet. the voltage at ovsens will be lower than the ovp input voltage by (i ovsens ? 6.04k) due to the ovp circuits quiescent current. the ovp input will be 200mv to 400mv higher than ovsens under normal operating conditions. when ovsens is below 6v, an in - ternal charge pump will drive ovgate to approximately 1.88 ? ovsens. this will enhance the n-channel mosfet and provide a low impedance connection to v bus or wall which will, in turn, power the ltc4098-3.6. if ovsens should rise above 6v (6.35v ovp input) due to a fault or use of an incorrect wall adapter, ovgate will be pulled to gnd, disabling the external fet to protect downstream circuitry. when the voltage drops below 6v again, the external mosfet will be reenabled. in an overvoltage condition, the ovsens pin will be clamped at 6v. the external 6.04k resistor must be sized appropriately to dissipate the resultant power. for example, a 1/10w 6.04k resistor can have at most p max ? 6.04k = 24v applied across its terminals. with the 6v at ovsens, the maximum overvoltage magnitude that this resistor can withstand is 30v. a 1/4w 6.04k resistor raises this value to 44v. walls absolute maximum cur - rent rating of 10ma imposes an upper protection limit of 66v. the charge pump output on ovgate has limited output drive capability. care must be taken to avoid leakage on this pin, as it may adversely affect operation. see the applications information section for examples of multiple input protection, reverse input protection, and a table of recommended components. ideal diode from bat to v out the ltc4098-3.6 has an internal ideal diode as well as a controller for an external ideal diode. both the internal and the external ideal diodes are always on and will respond quickly whenever v out drops below bat. if the load current increases beyond the power allowed from the switching regulator, additional power will be pulled from the battery via the ideal diodes. furthermore, if power to v bus (usb or wall power) is removed, then all of the application power will be provided by the bat - tery via the ideal diodes. the ideal diodes will be fast enough to keep v out from drooping with only the stor - age capacitance required for the switching regulator. the internal ideal diode consists of a precision amplifer that activates a large on-chip mosfet transistor whenever the voltage at v out is approximately 15mv (v fwd ) below the voltage at bat. within the amplifers linear range, the small-signal resistance of the ideal diode will be quite low, keeping the forward drop near 15mv. at higher current levels, the mosfet will be in full conduction. if additional conductance is needed, an external p-channel mosfet forward voltage (mv) (bat ? v out ) 0 current (ma) 600 1800 2000 2200 120 240 300 409836 f05 200 1400 1000 400 1600 0 1200 800 60 180 360 480 420 vishay si2333 external ideal diode ltc4098-3.6 ideal diode on semiconductor mbrm120lt3 figure 5. ideal diode v-i characteristics opera t ion
ltc4098-3.6 409836f transistor may be added from bat to v out . the idgate pin of the ltc4098-3.6 drives the gate of the external p-chan - nel mosfet transistor for automatic ideal diode control. the source of the external p-channel mosfet should be connected to v out and the drain should be connected to bat. capable of driving a 1nf load, the idgate pin can control an external p-channel mosfet transistor having an on-resistance of 30m or lower. figure 5 shows the decreased forward voltage compared to a conventional schottky diode. suspend ldo the ltc4098-3.6 provides a small amount of power to v out in suspend mode by including an ldo from v bus to v out . this ldo will prevent the battery from running down when the portable product has access to a suspended usb port. regulating at 3.8v, this ldo only becomes active when the switching converter is disabled. in accordance with the usb specifcation, the input to the ldo is current limited so that it will not exceed the low power or high power suspend specifcation. if the load on v out exceeds the suspend cur - rent limit, the additional current will come from the battery via the ideal diodes. the suspend ldo sends a scaled copy of the v bus current to the clprog pin, which will servo to approximately 100mv in this mode. thus, the high power and low power suspend settings are related to the levels programmed by the same resistor for 1x and 5x modes. battery charger the ltc4098-3.6 includes a constant-current/constant- voltage battery charger with automatic recharge, automatic termination by safety timer and thermistor sensor input for out-of-temperature charge pausing. the charger begins charging in full power constant-cur - rent mode. the current delivered to the battery will try to reach 1030v/r prog . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. the external load will always be prioritized over the bat - tery charge current. the usb current limit programming will always be observed and only additional power will be available to charge the battery. when system loads are light, battery charge current will be maximized. charge termination th e battery charger has a built-in safety timer. once the voltage on the battery reaches the preprogrammed foat voltage of 3.600v, the charger will regulate the battery volt - age there and the charge current will decrease naturally. once the charger detects that the battery has reached 3.600v, the 1-hour safety timer is started. after the safety timer expires, charging of the battery will discontinue and no more current will be delivered. automatic recharge once the battery charger terminates, it will remain off drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a charge cycle will au - tomatically begin when the battery voltage falls below v rechrg (typically 3.5v). in the event that the safety timer is running when the battery voltage falls below v rechrg , it will reset back to zero. to prevent brief excursions below v rechrg from resetting the safety timer, the battery voltage must be below v rechrg for more than 1.5ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g., v bus is removed and then replaced) or if the charger is momentarily disabled using the d2 pin. charge current the charge current is programmed using a single resistor from prog to ground. 1/1030th of the battery charge cur - rent is delivered to prog, which will attempt to servo to 1.000v. thus, the battery charge current will try to reach 1030 times the current in the prog pin. the program resistor and the charge current are calculated using the following equations: r v i i v r p rog ch g ch g p rog = = 1030 1030 , in either the constant-current or constant-voltage charg- ing modes, the voltage at the prog pin will be propor- tional to the actual charge current delivered to the battery. the charge current can be determined at any time opera t ion
ltc4098-3.6 409836f by monitoring the prog pin voltage and using the fol - lowing equation: i v r bat p rog p rog = ? 1030 in many cases, the actual battery charge current, i bat , will be lower than the programmed current, i chg , due to limited input power available and prioritization to the system load drawn from v out . charge status indication the chrg pin indicates the status of the battery charger. four possible states are represented by chrg which include charging, not charging (or foat charge current less than programmed end of charge indication current), unrespon - sive battery and battery temperature out of range. the signal at the chrg pin can be easily recognized as one of the above four states by either a human or a mi - croprocessor. an open-drain output, the chrg pin can drive an indicator led through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. to make the chrg pin easily recognized by both humans and microprocessors, the pin is either a dc signal of on for charging, off for not charging or it is switched at high frequency (35khz) to indicate an ntc fault. while switching at 35khz, its duty cycle is modulated at a slow rate that can be recognized by a human. when charging begins, chrg is pulled low and remains low for the duration of a normal charge cycle. when charge current drops to 1/10th the value programmed by r prog , the chrg pin is released (hi-z). the chrg pin does not respond to the c/10 threshold if the ltc4098-3.6 is in v bus current limit. this prevents false end-of-charge indications due to insuffcient power available to the battery charger. if a fault occurs while charging, the pin is switched at 35khz. while switching, its duty cycle is modulated between a high and low value at a very low frequency. the low and high duty cycles are disparate enough to make an led appear to be on or off thus giving the appearance of blinking. each of the two faults has its own unique blink rate for human recognition as well as two unique duty cycles for machine recognition. table 2 illustrates the four possible states of the chrg pin when the battery charger is active. table 2. chrg signal status frequency modulation (blink) frequency duty cycles charging 0hz 0hz (low z) 100% i bat < c/10 0hz 0hz (hi-z) 0% ntc fault 35khz 1.5hz at 50% 6.25% or 93.75% bad battery 35khz 6.1hz at 50% 12.5% or 87.5% notice that an ntc fault is represented by a 35khz pulse train whose duty cycle toggles between 6.25% and 93.75% at a 1.5hz rate. a human will easily recognize the 1.5hz rate as a slow blinking which indicates the out of range battery temperature while a microprocessor will be able to decode either the 6.25% or 93.75% duty cycles as an ntc fault. if a battery is found to be unresponsive to charging (i.e., its voltage remains below 2.85v for 1/2 hour), the chrg pin gives the battery fault indication. for this fault, a human would easily recognize the frantic 6.1hz fast blink of the led while a microprocessor would be able to decode either the 12.5% or 87.5% duty cycles as a bad cell fault. because the ltc4098-3.6 is a 3-terminal powerpath product, system load is always prioritized over battery charging. due to excessive system load, there may not be suffcient power to charge the battery beyond the bad- cell threshold voltage within the bad-cell timeout period. in this case the battery charger will falsely indicate a bad cell. system software may then reduce the load and reset the battery charger to try again. although very improbable, it is possible that a duty cycle reading could be taken at the bright-dim transition (low duty cycle to high duty cycle). when this happens the duty cycle reading will be precisely 50%. if the duty cycle reading is 50%, system software should disqualify it and take a new duty cycle reading. opera t ion
ltc4098-3.6 409836f ntc thermistor the battery temperature is measured by placing a nega - tive temperature coeffcient (ntc) thermistor close to the battery pack. the ntc circuitry is shown in the block diagram. to use this feature, connect the ntc thermistor, r ntc , between the ntc pin and ground and a bias resistor, r nom , from ntcbias to ntc. r nom should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r25). the ltc4098-3.6 will pause charging when the resistance of the ntc thermistor drops to 0.25 times the value of r25 or approximately 25k (for a vishay curve 1 thermistor, this corresponds to approximately 60c). if the battery charger is in constant-voltage (foat) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. as the temperature drops, the resistance of the ntc thermistor rises. the ltc4098-3.6 is also designed to pause charging when the value of the ntc thermistor increases to 3.26 times the value of r25. for a vishay curve 1 thermistor, this resistance, 326k, corresponds to approximately 0c. the hot and cold comparators each have approximately 3c of hysteresis to prevent oscilla - tion about the trip point. grounding the ntc pin disables all ntc functionality. figure 6 is a fow chart representation of the battery charger algorithm employed by the ltc4098-3.6. thermal regulation to prevent thermal damage to the ltc4098-3.6 or sur - rounding components, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to approximately 110c. ther - mal regulation protects the ltc4098-3.6 from excessive temperature due to high power operation or high ambi - ent thermal conditions, and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the ltc4098-3.6 or external components. the beneft of the ltc4098-3.6 thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions for a given application with the assurance that the charger will automatically reduce the current in worst-case conditions. shutdown mode the usb switching regulator is enabled whenever v bus is above the uvlo voltage and the ltc4098-3.6 is not in one of the two usb suspend modes (500a or 2.5ma). when power is available from both the usb and high voltage inputs, the high voltage regulator is prioritized and the usb switching regulator is disabled. the ideal diode is enabled at all times and cannot be disabled. opera t ion
ltc4098-3.6 0 409836f clear event timer ntc out of range chrg currently hi-z indicate ntc fault at chrg battery state charge at 1030v/r prog rate pause event timer pause event timer charge with fixed voltage (v float ) run event timer run event timer assert chrg low power on/ enable charger timer > 30 minutes timer > 1 hour bat > 2.85v bat < v rechrg i bat < c/10 no no yes yes yes yes yes yes no no bat > v float ? e bat < 2.85v 2.85v < bat < v float ? e no no no no inhibit charging stop charging indicate battery fault at chrg bat rising through v rechrg bat falling through v rechrg chrg high-z chrg hi-z 40981 f06 no yes yes inhibit charging yes figure 6. battery charger state diagram opera t ion
ltc4098-3.6 409836f clprog resistor and capacitor as described in the bat-track input current limited step down switching regulator section, the resistor on the clprog pin determines the average input current limit in each of the fve current limit modes. the input cur - rent will be comprised of two components, the current that is used to drive v out and the quiescent current of the switching regulator. to ensure that the total average input current remains below the usb specifcation, both components of input current should be considered. the electrical characteristics table gives the typical values for quiescent currents in all settings as well as current limit programming accuracy. to get as close to the 500ma or 100ma specifcations as possible, a precision resistor should be used. an averaging capacitor is required in parallel with the resistor so that the switching regulator can determine the average input current. this capacitor also provides the dominant pole for the feedback loop when current limit is reached. to ensure stability, the capacitor on clprog should be 0.1f or larger. choosing the inductor because the input voltage range and output voltage range of the powerpath switching regulator are both fairly narrow, the ltc4098-3.6 was designed for a specifc inductance value of 3.3h. some inductors which may be suitable for this application are listed in table 3. v bus and v out bypass capacitors the style and value of capacitors used with the ltc4098 -3.6 determine several important parameters such as regulator control loop stability and input volt - age ripple. because the ltc4098-3.6 uses a step-down switching power supply from v bus to v out , its input current waveform contains high frequency components. it is strongly recommended that a low equivalent series resistance (esr) multilayer ceramic capacitor be used to bypass v bus . tantalum and aluminum capacitors are not recommended because of their high esr. the value of the capacitor on v bus directly controls the amount of input ripple for a given load current. increasing the size of this capacitor will reduce the input ripple. the usb specifcation allows a maximum of 10f to be con - nected directly across the usb power bus. if additional capacitance is required for noise performance, it may be connected directly to the v bus pin when using the ovp feature of the ltc4098-3.6 . this extra capacitance will be soft-connected over several milliseconds to limit inrush current and avoid excessive transient voltage drops on the bus. to prevent large v out voltage steps during transient load conditions, it is also recommended that a ceramic capacitor be used to bypass v out . the output capacitor is used in the compensation of the switching regulator. at least 10f with low esr are required on v out . additional capacitance will improve load transient performance and stability. table 3. recommended inductors for the ltc4098-3.6 inductor type l (h) max i dc (a) max dcr ( ) size in mm (l w h) manufacturer lps4018 3.3 2.2 0.08 3.9 3.9 1.7 coilcraft www.coilcraft.com d53lc db318c 3.3 3.3 2.26 1.55 0.034 0.070 5 5 3 3.8 3.8 1.8 toko www.toko.com we-tpc type m1 3.3 1.95 0.065 4.8 4.8 1.8 wrth elektronik www.we-online.com cdrh6d12 cdrh6d38 3.3 3.3 2.2 3.5 0.0625 0.020 6.7 6.7 1.5 7 7 4 sumida www.sumida.com applica t ions in f orma t ion
ltc4098-3.6 409836f multilayer ceramic chip capacitors typically have excep - tional esr performance. mlccs combined with a tight board layout and an unbroken ground plane will yield very good performance and low emi emissions. there are several types of ceramic capacitors avail - able each having considerably different characteristics. for example, x7r ceramic capacitors have the best voltage and temperature stability. x5r ceramic capacitors have apparently higher packing density but poorer performance over their rated voltage and temperature ranges. y5v ceramic capacitors have the highest packing density, but must be used with caution, because of their extreme nonlinear characteristic of capacitance versus voltage. the actual in-circuit capacitance of a ceramic capacitor should be measured with a small ac signal and dc bias as is expected in-circuit. many vendors specify the capacitance versus voltage with a 1v rms ac test signal and, as a result, over state the capacitance that the capacitor will present in the application. using similar operating conditions as the application, the user must measure or request from the vendor the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. overprogramming the battery charger the usb high power specifcation allows for up to 2.5w to be drawn from the usb port. the switching regulator transforms the voltage at v bus to just above the voltage at bat with high effciency, while limiting power to less than the amount programmed at clprog. the charger should be programmed (with the prog pin) to deliver the maximum safe charging current without regard to the usb specifcations. if there is insuffcient current available to charge the battery at the programmed rate, it will reduce charge current until the system load on v out is satisfed and the v bus current limit is satisfed. programming the charger for more current than is available will not cause the average input current limit to be violated. it will merely allow the battery charger to make use of all available power to charge the battery as quickly as possible, and with minimal power dissipation within the charger. overvoltage protection it is possible to protect both v bus and wall from over - voltage damage with several additional components, as shown in figure 7. schottky diodes d1 and d2 pass the larger of v1 and v2 to r1 and ovsens. if either v1 or v2 exceeds 6v plus v f(schottky) , ovgate will be pulled to gnd and both the wall and usb inputs will be protected. each input is protected up to the drain-source breakdown, bvdss, of mn1 and mn2. r1 must also be rated for the power dissipated during maximum overvoltage. see the operations section for an explanation of this calculation. table 4 shows some n-channel mosfets that may be suitable for overvoltage protection. r1 c1 d1 v1 v2 d2 mn1 mn2 409836 f07 wall ovsens ovgate ltc4098-3.6 v bus figure 7. dual input overvoltage protection applica t ions in f orma t ion table 4. recommended ovp mosfets n-channel mosfet bvdss r on package si2302ads 20v 70m sot-23 irlml2502 20v 35m sot-23 si1472dh 30v 65m sc70-6 ntljs4114n 30v 20m 2mm 2mm dfn fdn372s 30v 45m sot-23
ltc4098-3.6 409836f adjustment resistor, both the upper and the lower tempera - ture trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. examples of each technique follow. ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. the vishay-dale thermistor nths0603n011-n1003f, used in the following examples, has a nominal value of 100k and follows the vishay curve 1 resistance-temperature characteristic. in the explanation below, the following notation is used. r25 = value of the thermistor at 25c r ntc|cold = value of thermistor at the cold trip point r ntc|hot = value of thermistor at the hot trip point a cold = ratio of r ntc|cold to r25 a hot = ratio of r ntc|hot to r25 r nom = primary thermistor bias resistor (see figure 9a) r1 = optional temperature range adjustment resistor (see figure 9b) the trip points for the ltc4098-3.6s temperature quali - fcation are internally programmed at 0.199 ? ntcbias for the hot threshold and 0.765 ? ntcbias for the cold threshold. therefore, the hot trip point is set when: r r r nt cbi as nt cbi as nt c hot nom nt c hot | | ? . ? + = 0 199 and the cold trip point is set when: r r r nt cbi as nt cbi nt c c ol d nom nt c c ol d | | ? . ? + = 0 765 a as r 2 r1 usb/wall adapter 409836 f08 c1 d1 mn1 mp1 v bus positive protection up to bvdss of mn1 v bus negative protection up to bvdss of mp1 v bus ovsens ovgate ltc4098-3.6 figure 8. dual-polarity voltage protection reverse voltage protection the ltc4098-3.6 can also be easily protected against the application of reverse voltage, as shown in figure 8. d1 and r1 are necessary to limit the maximum vgs seen by mp1 during positive overvoltage events. d1s breakdown voltage must be safely below mp1s bvgs. the circuit shown in figure 8 offers forward voltage protection up to mn1s bvdss and reverse voltage protection up to mp1s bvdss. applica t ions in f orma t ion alternate ntc thermistors and biasing the ltc4098-3.6 provides temperature-qualifed charging if a grounded thermistor and a bias resistor are connected to ntc and ntcbias. by using a bias resistor whose value is equal to the room temperature resistance of the thermistor (r25) the upper and lower temperatures are preprogrammed to approximately 60c and 0c, respec - tively (assuming a vishay curve 1 thermistor). the upper and lower temperature thresholds can be ad - justed by either a modifcation of the bias resistor value or by adding a second adjustment resistor to the circuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modifed but not both. the other trip point will be determined by the characteristics of the thermistor. using the bias resistor in addition to an
ltc4098-3.6 409836f by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direction. the temperature span will change somewhat due to the nonlinear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: r r r r nom hot nom co ld = = a a 0 2 5 25 3 2 6 25 . ? . ? where a hot and a cold are the resistance ratios at the desired hot and cold trip points. note that these equations solving these equations for r ntc|cold and r ntc|hot results in the following: r ntc|hot = 0.25 ? r nom and r ntc|cold = 3.26 ? r nom by setting r nom equal to r25, the previous equations result in a hot = 0.25 and a cold = 3.26. referencing these ratios to the vishay resistance-temperature curve 1 chart gives a hot trip point of about 60c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 60c. ? + ? + r nom 100k r ntc 100k ntc 0.1v ntc_enable 409836 f09a ltc4098-3.6 ntc block too_cold too_hot 0.765 ? ntcbias 0.199 ? ntcbias ? + 5 ntcbias 4 t ? + ? + r nom 102k r ntc 100k r1 8.06k ntc 0.1v ntc_enable 409836 f09b too_cold too_hot 0.765 ? ntcbias 0.199 ? ntcbias ? + 5 t ntcbias 4 ltc4098-3.6 ntc block (9a) (9b) figure 9. ntc circuits applica t ions in f orma t ion
ltc4098-3.6 409836f are linked. therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the ic. consider an example where a 70c hot trip point is desired. from the vishay curve 1 r-t characteristics, a hot is 0.1753 at 70c. using the previous equation, r nom should be set to 70.4k. with this value of r nom , the cold trip point is 7c. notice that the span is now 63c rather than the previous 60c. this is due to the decrease in temperature gain of the thermistor as absolute temperature increases. the upper and lower temperature trip points can be inde - pendently programmed by using an additional bias resistor as shown in figure 9b. the following formulas can be used to compute the values of r nom and r1: r r r r r nom co ld hot nom hot = = a a a C . ? . ? C ? 3 0 1 25 1 0 25 25 5 for example, to set the trip points to 0c and 70c with a vishay curve 1 thermistor choose: r k k nom = = 3 2 6 0 1753 3 0 1 100 102 5 . C . . ? . the nearest 1% value is 102k: r1 = 0.25 ? 102k C 0.1753 ? 100k = 7.97k the nearest 1% value is 8.06k. the fnal circuit is shown in figure 9b and results in an upper trip point of 70c and a lower trip point of 0c. usb inrush limiting the usb specifcation allows at most 10f of downstream capacitance to be hot-plugged into a usb hub. in most ltc4098-3.6 applications, 10f should be enough to provide adequate fltering on v bus . if more capacitance is required, the ovp circuit will provide adequate soft-connect time to prevent excessive inrush currents. an additional 22f on the v bus pin will gener - ally contribute less than 100ma to the hot-plug inrush current. voltage overshoot on v bus may sometimes be observed when connecting the ltc4098-3.6 to a lab power supply. this overshoot is caused by long leads from the power supply to v bus . twisting the wires together from the sup - ply to v bus can greatly reduce the parasitic inductance of these long leads, and keep the voltage at v bus to safe levels. usb cables are generally manufactured with the power leads in close proximity, and thus fairly low parasitic inductance. applica t ions in f orma t ion
ltc4098-3.6 409836f board layout considerations the exposed pad on the backside of the ltc4098-3.6 pack - age must be securely soldered to the pc board ground. this is the primary ground pin in the package and it serves as the return path for both the control circuitry and the synchronous rectifer. furthermore, due to its high frequency switching circuitry, it is imperative that the input capacitor, inductor, and output capacitor be as close to the ltc4098-3.6 as pos - sible and that there be an unbroken ground plane under the ltc4098-3.6 and all of its external high frequency components. high frequency currents, such as the input current on the ltc4098-3.6, tend to fnd their way on the ground plane along a mirror path directly beneath the incident path on the top of the board. if there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. if high frequency currents are not allowed to fow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur (see figure 10). there should be a group of vias directly under the grounded backside leading directly down to an internal ground plane. to minimize parasitic inductance, the ground plane should be as close as possible to the top plane of the pc board (layer 2). the idgate pin for the external ideal diode controller has extremely limited drive current. care must be taken to minimize leakage to adjacent pc board traces. 100na of leakage from this pin will introduce an additional offset to the ideal diode of approximately 10mv. to minimize leakage, the trace can be guarded on the pc board by surrounding it with v out connected metal, which should generally be less than one volt higher than idgate. battery charger stability considerations the ltc4098-3.6s battery charger contains both a con - stant-voltage and a constant-current control loop. the constant-voltage loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. high value, low esr multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 22f may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. furthermore, a 100f mlcc in series with a 0.3 resistor or a 100f os-con capacitor from bat to gnd is required to prevent oscillation when the battery is disconnected. in constant-current mode, the prog pin is in the feed - back loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the charger is stable with program resistor values as high as 25k. however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the fol - lowing equation should be used to calculate the maximum resistance value for r prog : r kh z c p rog p rog 1 2 100 ? ? applica t ions in f orma t ion figure 10. ground currents follow their incident path at high speed. slices in the ground plane cause high voltage and increased emissions 409836 f10
ltc4098-3.6 409836f high effciency usb/2a automotive battery charger with overvoltage protection and low battery start-up v bus v c wall acpr automotive, firewire, etc. usb to c to c system load m2 c2 10f 0805 c1 4.7f c7 68nf c5 10f 0805 c4 22f c6 0.47f c3 0.1f 0603 r4 100k r9 499k r11 150k 4 2 3 7 3 7 9, 21 6 9 20 18 19 14 12 10 11 11 1 8 5 10 13 d3 m3 r6 3.01k r7 681 m1 l1 3.3h l2 10h 409836 ta02 clprog prog ltc4098-3.6 lt3480 gnd sw batsens ovgate ovsens d0-d2 chrg ntcbias ntc 2 1 15-17 8 4 5 v out idgate bat lifepo 4 + r5 100k t m1, m2: vishay-siliconix si2333cds m3: on semiconductor ntljs4114n r5: vishay-dale nths0603n011-n1003f r10 40.2k r8 100k r3 6.04k rt v in run/ss pg gnd v c bd sw fb boost 3 t ypical applica t ions
ltc4098-3.6 409836f v bus ovgate wall acpr 5v wall adapter usb to c to c system load m6 c2 10f 0805 c1 10f 0805 c4 10f 0805 c3 0.1f 0603 r4 100k 3 7 9, 21 6 2 18 19 14 12 10 11 13 d4 d3 d2 d1 r6 3.01k r7 681 r2 m5 l1 3.3h 409836 ta03 clprog prog ltc4098-3.6 gnd sw batsens ovsense d0-d2 chrg ntcbias ntc 1 15-17 8 4 5 v out idgate bat + m3 m4 r5 100k t r1 m1 m2 r3 6.04k m1, m2, m5, m6: vishay-siliconix si2333cds m3, m4: fairchild semi fdn372s r5: vishay-dale nths0603n011-n1003f d1, d2: nxp bat54c d3, d4: on semiconductor mnbz5232blt1g 3 lifepo 4 usb/wall adapter battery charger with dual overvoltage protection, reverse-voltage protection and low battery start-up t ypical applica t ions usb/automotive switching battery charger with automatic current limiting on both inputs v bus v c wall acpr automotive, firewire, etc. usb wall adapter to c to c system load c3 10f 0805 c5 10f 0805 c1 4.7f c2 0.1f 10v c4 0.1f 0603 r2 100k r1 27.4k 1 7 8 9 3 7 9, 21 6 3 20 18 19 14 12 10 11 2 6 5 4 13 m1 r4 3.01k r5 681 d1 l2 3.3h l1 4.7h 409836 ta04 clprog prog ltc4098-3.6 lt3653 gnd sw batsens ovgate ovsens d0-d2 chrg ntcbias ntc 2 1 15-17 8 4 5 v out idgate bat v out i sense lifepo 4 + r3 100k t r6 6.04k v in i lim gnd v c hvok sw boost m1: on semiconductor ntljs4114n r3: vishay-dale nths0603n011-n1003f 3
ltc4098-3.6 409836f t ypical applica t ions low component count usb and automotive high effciency power manager v bus v c wall acpr automotive, firewire, etc. usb wall adapter to c to c system load c3 10f 0805 c1 4.7f c2 0.1f 10v c4 0.1f 0603 r1 27.4k 1 7 8 9 3 7 9, 21 6 3 20 18 19 14 10 11 12 2 6 5 4 13 5 r2 3.01k r3 681 d1 l2 3.3h l1 4.7h 409836 ta05 clprog prog ltc4098-3.6 lt3653 gnd sw batsens ovgate ovsens d0-d2 chrg ntcbias ntc 2 1 15-17 8 4 idgate bat v out v out i sense + v in i lim gnd v c hvok sw boost c5 10f 0805 3 lifepo 4
ltc4098-3.6 0 409836f t ypical applica t ions v bus v c wall acpr automotive, firewire, etc. usb to c to c c3 10f 0805 c1 4.7f 50v c2 0.1f, 10v c4 0.1f 0603 r2 27.4k 1 7 8 9 3 7 9, 21 6 3 20 18 19 14 2 6 5 4 13 m2 r7 3.01k r8 681 d2 l2 3.3h l1 4.7h 409836 ta06 clprog prog ltc4098-3.6 lt3653 gnd sw batsens ovgate ovsens d0-d2 chrg ntcbias ntc 2 1 15-17 8 4 5 v out idgate bat v out i sense lifepo 4 r4 6.04k v in i lim gnd v c hvok sw boost 3 m1: vishay-siliconix si2333cds m2: on semiconductor ntljs4114n r6: vishay-dale nths0603n011-n1003f system load m1 c5 10f 0805 12 10 11 r5 100k r6 100k t + high effciency usb automotive battery charger with overvoltage protection and low battery start-up
ltc4098-3.6 409836f information furnished by linear technology c orporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology c orporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 3.00 p 0.10 1.50 ref 4.00 p 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref 0.75 p 0.05 r = 0.115 typ pin 1 notch r = 0.20 or 0.25 s 45 o chamfer 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (udc20) qfn 1106 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p 0.05 0.25 p 0.05 2.50 ref 3.10 p 0.05 4.50 p 0.05 1.50 ref 2.10 p 0.05 3.50 p 0.05 package outline r = 0.05 typ 1.65 p 0.10 2.65 p 0.10 1.65 p 0.05 udc package 20-lead plastic qfn (3mm s 4mm) (reference ltc dwg # 05-08-1742 rev ?) 2.65 p 0.05 0.50 bsc pac k a g e d escrip t ion
ltc4098-3.6 409836f linear technology corporation 1630 mc c arthy blvd., milpitas, c a 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0710 ? printed in usa part number description comments ltc3555/ ltc3555-1/ ltc3555-3 switching usb power manager with li-ion/polymer charger, triple synchronous buck converter plus ldo complete multifunction pmic: switch mode power manager and three buck regulators plus ldo charge current programmable up to 1.5a from wall adapter input, synchronous buck converters effciency >95%, adj outputs: 0.8v to 3.6v at 400ma/400ma/1a bat-track adaptive output control, 200m ideal diode, 4mm 5mm qfn-28 package ltc3576/ ltc3576-1 switching power manager with usb on-the-go plus triple step-down dc/dcs complete multifunction pmic: bidirectional switching power manager plus three buck regulators plus ldo, adj output down to 0.8v at 400ma/400ma/1a, overvoltage protection, usb on-the-go, charge current programmable up to 1.5a from wall adapter input, thermal regulation, i 2 c, high voltage bat-track buck interface, 180m ideal diode; 4mm 6mm qfn-38 package ltc4088 high effciency usb power manager and battery charger maximizes available power from usb port, bat-track, instant-on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, 4mm 3mm dfn-14 package ltc4090/ ltc4090-5 high voltage usb power manager with ideal diode controller and high effciency li-ion battery charger high effciency 1.2a charger from 6v to 38v (60v max) input. charges single-cell li-ion/ polymer batteries directly from a usb port, thermal regulation, 200m ideal diode with <50m option, 6mm 3mm dfn-22 package. bat-track adaptive output control ltc4099 i 2 c controlled usb switch mode power manager with ovp 66v ovp. i 2 c for control and status readback, overtemperature battery conditioner for added battery safety margin, maximizes available power from usb port, bat-track, instant- on operation, 1.5a maximum charge current from wall, 600ma charge current from usb, 180m ideal diode with <50m option; 3mm 4mm qfn-20 package ltc4413 dual ideal diodes 3mm 3mm dfn package, low loss replacement for oring diodes lt3652hv power tracking 2a battery charger high v in : 34v operating, 40v abs max, 2a monolithic nonsynchronous buck charger with input voltage regulation loop. programmable float voltage up to 18v. rela t e d par t s t ypical applica t ion 1.5a standalone lifep0 4 charger v bus v c wall acpr wall adapter system load c1 10f 0805 c3 10f 0805 c2 0.1f 0603 3 7 9, 21 6 4 5 20 18 19 14 12 10 11 13 2 r2 2k r3 681 l1 3.3h 409836 ta07 clprog prog ltc4098-3.6 gnd sw ntcbias batsens ntc d2 chrg d0 ovsens ovgate d1 1 15 16 8 17 v out idgate bat + r4 100k r1 2k r5 100k t lifepo 4 on off

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